LTD Defect Metrology Engineer

Role details

Job Details: Job Description: At Intel's Logic Technology Development (LTD) we have continued to extend Moore's law to be world leaders in computing technology. To achieve the necessary scaling of our semiconductor manufacturing process, we have led the industry in developing enhancements such as strained silicon for carrier transport enhancement, high-k metal gates, and FINFETs. LTD has been at the center of every new development that has kept Moore's Law moving forward.

Defect Metrology plays a key role in the development of every new silicon process development. Our analysis builds the plan that allows LTD to take technology from the research phase to the high-volume manufacturing phase while maintaining high-quality standards. In the MIE organization, we engineer world-class yields on D1 processes by driving defects down to Best-in-Class targets.

As a Defect Metrology engineer, you will be responsible for identifying all the defects that impact yield and performance in an advanced silicon process technology. You will characterize the process using cutting-edge metrology tools. With this characterization, you will be responsible for creating the defect reduction roadmap.

You will then work directly with modules and integration to drive that roadmap by developing and qualifying process fixes. This role provides an opportunity to influence Intel's future process technologies that will keep Moore's Law moving forward. Responsibilities/Duties include but not limited to: Provide navigation and leadership to meet Intel's yield objectives utilizing state of the art metrology tools and QTMs.

Organizing and presenting defect summaries to LTD engineering teams. Partnering with Intel Integration, Yield, and failure analysis labs to provide root cause for all defect issues. Institute ramp to manufacturing volumes to demonstrate the technology meets requirements while simultaneously transferring the technology to counterparts in manufacturing via the Copy Exactly Methodology.

Hold the team and collaborators accountable for quality through IMT and FTs. Work collaboratively as a part of the overall TD Defect metrology group. Role-model and establish a team culture of trust, collaboration, safety, accountability, and excellence.

Build strong relationships with other LTD process and design teams based on mutual trust and respect. An ideal candidate should be willing to demonstrate the below behavioral traits : Data analysis and problem debug skills. Excellent communication skills.

Understand and adhere to key Intel values Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and internship experience.

Minimum Qualifications

), semiconductor and or transistor device physics, and design of experiments. Demonstrate experience of Statistical Process Control SPC or Design of Experiments (DOE) principles. Semiconductor physics.

Semiconductor processing. Yield Improvement, Defect Improvement Brightfield, Darkfield, Voltage Contrast (VC) Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry.

It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . 00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.

Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

• Job posting details (such as work model, location or time type) are subject to change. • ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process.

Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.